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Driving Higher PV Inverter Efficiencies with Customizable System-on-Chip

Semiconductor technological advances are giving PV designers the ability to drive higher efficiencies, thus maximizing precious harvested energy. Integration of numerous board-level components is key to driving lower power consumption and BOS. Newly introduced customizable System-on-Chip (cSoC) integrates control, temperature/power sensing and management, and communications functions into a single, low-power Integrated Circuit (IC) by including an ARM microcontroller, programmable analog and Field Programmable Gate Array (FPGA). This article explores innovative design techniques and the usage of cSoC to develop and bring to market cost and power sensitive, next-generation PV string and microinverters.

By Rufino Olay



Rising interest in the renewable energy market is enticing a growing number of companies to utilize their core competencies in developing innovative solutions necessary in meeting PV volume and capacity projections. In order to reach grid parity and beyond, manufacturers are utilizing or developing new techniques, devices and procedures to improve overall efficiencies and reduce power consumption and costs. Current estimates for PV inverter costs account for approximately 7-10% of system hardware. Module costs are projected to decrease at a faster rate, thus the inverter cost percentage is forecasted to increase to 12% of system hardware by 2015.1) Consequently, PV inverter designers are facing the challenge by partnering with semiconductor companies to integrate higher level functions and algorithms coupled with a wider array of mixed signal components into the latest generation of ICs.

For the past 30 years, string inverters have been the prevailing inverter topology and continue to be a viable solution for many deployments. In recent years, numerous new inverter topologies have started making inroads as alternatives to string inverters including but not limited to; microinverters, power optimizers, mini-inverters and inverter-less power systems. Higher efficiency rates, together with requirements for extended warranties and value added features ranging from system monitoring to web connectivity to theft alert to name a few, are being incorporated for differentiation in an increasingly crowded field of companies and products.

Regardless of the technology though, the main objective is to convert as much precious harvested energy from a Direct Current (DC) format and transform and condition it into either useable Alternating Current (AC) to be feed back onto the grid or into an off-grid DC storage system for later use.

The main component of a PV inverter is a microprocessor or microcontroller employed in system management for features such as power switching, grid and temperature sensing, data logging, display and communication interfaces, battery charging management, and fan control. A variety of power control algorithms are utilized to accomplish several system tasks including Pulse Width Modulation (PWM), Maximum Power Point Tracking (MPPT) and Power Factor Correction (PFC). In most cases, designers are applying their expertise to deploy different degrees of implementation in order to increase product competitiveness.


Meeting the Particular Needs of PV Inverter Designers


Historically designers have had access to an assortment of real-time microcontrollers in different configurations, bit widths, processing power, embedded memory and peripherals for an assortment of embedded applications. Semiconductor manufacturers have recognized the particular needs of PV designers and have responded accordingly to develop power efficient processing platforms on which to bring to market next generation PV products. PV focused microcontroller platforms are increasingly adding single or dual core optimized computing engines coupled with a comprehensive feature set of mixed signal attributes such as Analog Digital Converters (ADC) and Digital to Analog Converters (DAC), PWM channels, voltage and temperature monitors, as well as connectivity interfaces to address evolving communication standards. These flexible platforms are being introduced from a number of sources including startups, traditional microcontroller companies and Programmable Logic Device (PLD) focused companies.


Evolution of the Customizable System -on-Chip (cSoC)


The PV industry drive to lengthen warranties necessitates the scrutiny of each device used for numerous factors. Higher levels of system integration are a given, but longevity requirements of product availability and a company’s pedigree of providing high reliability are also considerations used in device selection.

It has been a long-known fact that integration increases reliability and reduces costs by consolidating system and supporting functions within as few components or ICs as possible. In the past decade, PLD manufacturers continue to improve their product portfolio to include computing cores in either hard/embedded or soft CPUs (Figure 1). The next stage of PLD development is a complete mixed signal platform optimized for particular needs--whether for low-power consumption applications, as in the case of PV inverters, or high computing platforms required in wireless infrastructure. In either case, selecting the right components is paramount to extracting the ideal balance of power and performance.



The system on a chip concept is the integration of numerous board-level components into a single monolithic or packaged IC in which hardware and software teams can co-develop their portion of the system and deploy results into a single platform IC. One approach, the flash based customizable system-on-chip (Figure 2), takes the concept even further and includes three major subgroups:


-Sense & Control

-Configurable Logic

The advantages of such an approach include more than just the integration cost savings, but also the increased reliability and power budget reduction. This common platform gives the design teams the ability to utilize available cSoC resources in system implementation trade-offs such as partitioning portions of a computational intensive algorithm for hardware acceleration or time division multiplexing to maximize gate logic usage and run the output to control or provide input to downstream state-machines or off-chip switching components. A flash-based architecture allows low overall power consumption and for live-at-power-up capability. At night, some use cases allow grid-tied inverters to be placed into sleep mode for energy conservation. Live-at-power-up ensures immediate system initiation and bring-up in order to maximize PV system output in early morning light conditions.




ARM has successfully become the leading Intellectual Property (IP) supplier with strong growth of ARM-based processor shipments in a variety of markets and devices including smart phones, tablets, set-top boxes and TVs with shipments of 6.2 billion units in 2010.2)

Included in the ARM processor IP portfolio is the Cortex™-M family of energy-efficient processors (Figure 3). Architected for power sensitive applications, the Cortex-M family is ideally suited for embedded mixed-signal devices in applications ranging from industrial control, smart metering, automotive, white goods, consumer products and medical applications. More than 40 companies have recognized the advantages of the Cortex-M family and have partnered with ARM to deliver on the promise of energy efficiency in microcontroller applications.

Inclusion of an ARM Cortex-M3 onto a cSoC platform ensures timing compliance across the AHB bus to different on-chip peripherals. Aside from the normal control plane processing functions, PV specific algorithms can be ported from a customer’s library into the proven Cortex-M3. For instance, the MPPT algorithm ensures optimum efficiency is achieved from the PV panels during shading occasions or age-induced degradation. The resulting current and voltage mismatches are compensated through an MPPT algorithm by introducing variable impedance in which to maximize energy transfer. Numerous IEEE technical papers have been presented that utilize different methods including Perturb and Observe (P&O), Incremental Conductance (INC), and constant voltage method or a variation of each. The mathematical portions of the MPPT can be partitioned into the configurable logic fabric for single cycle or pipelined processing depending on response time requirements, especially to avoid processing delay errors due to fast-changing conditions. PV inverter companies implement their own version of MPPT and can be considered one of the crown jewels in product differentiation when it comes to response time and efficiency.


Sense & Control


Monitoring and evaluating operating conditions are key to keeping a PV system at its peak performance and gives end-users and utilities visibility into potential failures prior to their occurrence, allowing them to act accordingly. On-chip resources such as high-voltage bipolar voltage monitors and Phase-Locked Loops (PLL) measure and compensate for frequency and phase-angle differences between the grid supply and inverter output. Grid voltage polarity is sampled at each cSoC ADC trigger and a zero cross flag can be set and registered.

Chassis or PV panel temperature monitoring keeps tabs on ambient operating conditions and data is capable of being stored in on-chip or off-chip memory dependant on length of data storage requirements. Additionally, real-time or planned time of day data transfers, via on-board communication interfaces, can be adjusted given scheduling constraints or processing bandwidth.



Stand-alone PV systems have their own challenges especially when it comes to battery charging management. Constant monitoring and adaptive trickle charging are functions necessary for optimal battery performance. Careful avoidance of stressing the battery above charging capacity or running the battery past a specified operational output level ensures battery lifetime longevity and removes early replacement or unplanned maintenance. Individual battery cells should also be monitored for variation in charge resistance due to age. Equalization techniques restore unbalanced cells and increase charge acceptance. Monitoring battery charging temperature is available via the signal conditioning block (SBC) with a ¼ ºC resolution.


Configurable Logic


Hardware acceleration in PLDs has been recognized as a viable approach to increasing data computational throughput. In essence, arithmetic co-processing is accomplished through the high frequency switching capability (typically greater than 300 MHz) and the parallel nature of an FPGA fabric.

Design techniques to maximize data processing abound and their implementation is dependent on logic cell or memory/RAM availability. For instance, pipelining different stages of a multiplier can ensure high throughput but may be unnecessary and is dependent on the processing needs of the system. Conversely, an extremely fast, pipelined multiplier can potentially be used to drive numerous low frequency state-machines, thus logic cell usage is kept to a minimum.

Another technique to implement fast multipliers is the utilization of on-chip dual-port RAM configured as a ROM.3) The predetermined results of the multiplier are placed into a RAM in one clock domain and the results read out on another. Constant and variable multipliers may be developed in this fashion and the address pointer acts as the arithmetic operators.

A Fast Fourier Transforms (FFT) of an inverter output voltage waveform performs signal quality analysis for Total Harmonic Distortion (THD). Results are then compared to grid waveforms and adjusted accordingly. Implementing the FFT algorithm is possible in either the Cortex-M3 or the Configurable Logic. Typically a hardware implementation is benchmarked in the tens of microseconds versus hundreds of microseconds when executed within a microcontroller. In either case, the realization path is design dependant, therefore, having the option of either hardware or software implementation, and the accompanying trade-off possibilities, is advantageous.

PWM is a necessity to efficiently control power switching components such as IGBTs and MOSFETs. Alternative PWM implementation is achievable and again dependent on system requirements.

Take for example, a system that requires the smallest footprint possible due to space constraints. In this scenario, the technique of resource sharing is utilized whereby a high performance PWM statemachine operates at frequencies in the multi-MHz range. The input of the PWM is controlled in a feedback loop from the analysis of the inverter output versus grid supply waveform. The high frequency PWM output is then placed into FIFOs that control the multiple KHz range switching elements (IGBTs or MOSFETs). This design technique is also suitable in applications where a single device controls multiple switching supplies such as mini-inverters (the inclusion of multiple microinverters within a single package).

Conversely, in systems with tight power budget requirements the approach is to integrate board level PWM devices into multiple on-chip low processing (KHz) PWM channels. This method immediately reduces off-chip power supply requirements and allows designers to customize the exact number of PWM channels and switching characteristics per the system specification. 



Semiconductor advances are allowing PV inverter designers to develop differentiated products with higher efficiencies and reliability, lower cost and longer warranties. ICs such as the customizable system-on-chip build on the promise of providing highly flexible development platforms (Figure 4) in which both hardware and software architects can co-develop system features and algorithms necessary to support the race towards grid parity.


Rufino Olay is Sr. Market Solutions Manager at Microsemi Corp where he helps customers realize their renewable energy-focused designs and applications. Olay began his career as a hardware engineer where he developed numerous FPGA-based designs and has worked in applications and marketing in the FPGA, wireless infrastructure and PV industries. In recent years, he has provided marketing for PV module and optimizer companies and is a former chairman of the Santa Clara Valley IEEE. Olay has a BSEE from San Jose State University.



1) IMS Research, “The World Market for Photovoltaic Inverters ? 2011 Edition,” p 30

2) Gartner, “Market Share Analysis: Semiconductor Intellectual Property, Worldwide, 2010,” March 30, 2011, p 5

3) “Using Fusion, IGLOO, and ProASIC3 RAM as Multipliers,” Application Note AC241, Microsemi, 2008.



For more information, please send your e-mails to pved@infothe.com.

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